The present invention relates to a manufacturing for and structure of semiconductor memory devices and particularly to dynamic type semiconductor memory devices such as DRAMs (Dynamic Random Access Memories) which have achieved high integrations and high performances in which trenches are installed within respective capacitor regions.
A dynamic type memory cell has extensively been used for a memory element since it can be integrated with high density. The dynamic type memory cell includes a single memory capacitor and a single switching transistor interconnected to the capacitor, as illustrated in FIG. 6. However, as high integrations of IC memory devices with high densities are advanced, an occupied area per memory cell is decreased and accordingly an electric charge amount to be stored in each capacitor is remarkably reduced. Therefore, the contents of some memory cells will erroneously be read.
To solve such a problem as described above, a trench is formed on a surface of a substrate of the memory capacitor region to increase the surface area. Therefore, the capacity of the memory capacitor is increased and an amount of electric charge is thus increased.
FIGS. 5(A) and 5(B) show a conventional 4M bit memory cell structure using a trench capacitor disclosed in a Japanese document of NIKKEI MICRODEVICES pages 16 through 19 published in the spring of 1985.
As shown in FIGS. 5(A) and 5(B), each transistor is enclosed with a separation oxidized film 42 located within a separation recess. A polycrystalline Si electrode 43 is formed inside of the oxidized film 42 with respect to the capacitor to constitute one electrode of the capacitor and is connected to a source for the transistor. A polycrystalline Si cell plate 45 sandwiched with a capacitor separation film 44 constitutes the other electrode of the capacitor. A drain D is connected to a bit line (B Line) via a contact hole 46.
In the above-described cell structure, both capacitor and transistor are formed in parallel to the bit line (B Line). In addition, a single trench is provided with both functions of an inter-element separation and of formation of the single capacitor.
In the above-described memory cell structure using the conventional trench capacitor, the connection between the capacitor and transistor cannot be carried out in a self alignment manner. In addition, the polycrystalline Si provides means for connecting the capacitor to the transistor. In order to form the capacitor and to separate electrically one of the memory elements from the adjacent memory element, a plurality of thin SiO.sub.2 films must accurately be formed within the respective polycrystallines Si located within the trenches. To achieve this, an extremely high and complicated IC manufacture technology are required. Furthermore, in the conventional memory cell structure using the trench capacitor, both occupying areas required to separate one of the memory elements from the adjacent memory element and required to form the capacitor are still large in order to manufacture an integrated memory device with a high density and with a sufficient memory capacity.